This invention generally relates to apparatuses and methods for modulating current/voltage response using multiple different semiconductor structures which create different SCR operable to influence an electrical signal path in different environments or modes. In particular, embodiments of the invention can have various implementations using different types of semiconductor structures which can be used, e.g., for implementing or using types of semiconductors that, by themselves, are normally susceptible to various types of radiation or electromagnetic interference effects. Embodiments of the invention provide various approaches to enable use of such semiconductor structures in various applications or environments including a radiation or electromagnetic interference environment.
Lateral Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistors (LDMOSFETs) are used because of their fast switching, high power capabilities. FIG. 1 represents a simplistic vertical cross-sectional view of an exemplary N-channel LDMOSFET 1 design/layout where a LDMOSFET structure is sliced parallel to a source and a drain and laterally along a channel (for reference, see FIG. 2, orientation of cutline AB used in FIG. 1). An exemplary N-channel LDMOSFET 1 as shown in FIG. 1 uses a first and second surface of a P substrate 101 (e.g., P doped silicon). On first surface, a conductive layer (e.g., metal) is disposed onto P substrate forming a substrate contact 117. On second surface (e.g., opposite surface of substrate contact 117), an N epitaxial layer 103 (e.g., N doped silicon) is disposed onto P substrate 101. On opposing surface of N-epitaxial layer 103 as P substrate 101, a region of opposite doping (N epitaxial layer uses P doping) is implanted/diffused to form P-body 105 (e.g., P body for source). To ensure Ohmic, e.g., resistive or electrical, contact to P body region, a higher P+ doped region is implanted/diffused into surface of P body region to form P+ body 111 (e.g., a body well contact region). After P doped regions (P body 105 and P+ body 111) are formed, an opposite doping of exemplary P body regions (e.g., N doping) is implanted/diffused into surface of P body 105 and adjacent to P+ body 111 forming an N+ body 109 region defining a source region and another N+ body is implanted/diffused into surface of N epitaxial layer 103 on opposing side of P substrate 101 forming an N+ body 107 defining a drain region where placement of N+ body is at a defined separation distance between P body 105 region and N+ body region (separation distance defines LDMOSFET's breakdown voltage). A gate dielectric 113 is disposed on top of and overlapping a portion of N+ body 109 extending laterally over P body 105 and overlapping a portion of N epitaxial layer 103. A conductive layer (e.g., polysilicon) is disposed on top of gate dielectric 113 to form a gate contact 115 (e.g., LDMOS gate contact). A region extending from N+ body across P body 105 to N epitaxial layer 103 underneath gate dielectric 113 defines a semi-conductive channel region (SCR) 123. Dashed arrow lines 125 represent an electrical current path that is formed during operation of exemplary N-channel LDMOSFET 1. Another conductive layer (e.g., metal) is disposed on top and overlapping a portion of P+ body 111 extending laterally over and covering a portion of N+ body 109 to form a source contact 121 (e.g., a LDMOS source contact). Another conductive layer (e.g., metal) is disposed on top of and covering a portion of N+ body 107 to form a drain contact 119 (e.g., LDMOS drain contact). Those steps provide a simplistic description of how an N-channel LDMOSFET 1 can be manufactured. P-channel LDMOSFETs (not shown) can be manufactured following similar steps but differs in design to an N-channel LDMOSFET 1 in that references to N doped regions (e.g., N epitaxial layer and N+ body) become P doped regions (e.g., P epitaxial layer and P+ body) and references to P doped regions (e.g., P substrate, P body and P+ body) become N doped regions (e.g., N substrate, N body, and N+ body).
Attempts have been made, including numerous modifications/improvements in design, layout, and fabrication of LDMOSFETs, to enhance electrical and radiation performance (e.g., increase power density, faster switching, enhanced radiation performance, etc.). Significant efforts have been devoted to resolve certain radiation issues (e.g., total ionizing dose (TID), single-event burnout (SEB); and single-event gate rupture (SEGR)).
Under some types of LDMOSFET operation, application of an appropriate gate voltage (a gate voltage greater than LDMOSFET's gate threshold voltage) forms a semi-conductive channel region between source and drain (an electrical conductive path) allowing current to flow (LDMOSFET is turned on). Higher gate voltages above threshold voltage equate to higher current flow. One effect of TID is to trap charge within gate dielectric, which in turn induces a shift in LDMOSFET gate threshold voltage (e.g., gate threshold voltage changes with TID). If TID-induced threshold voltage shifts become sufficiently large, LDMOSFETs can become non-functional (e.g., N-channel LDMOSFETs cannot be turned off and P-channel LDMOSFETs cannot be turned on without exceeding electrical specifications). Methods have been attempted to help resolve TID issues in LDMOSFETs. One method seeks to decrease gate dielectric thickness (e.g., thinner gate dielectric traps less charge but makes device more susceptible to SEGR). Another method entails controlling quality of gate dielectric (e.g., higher gate dielectric quality traps less charge) but higher quality also equates to higher costs. Another method entails exceeding gate voltage specifications to drive LDMOSFET (e.g., to turn-on or turn-off device) but applied voltages can rapidly exceed a safe operating range and higher voltages make devices more susceptible to SEGR.
FIG. 3 represents a cross-sectional view of a simplistic design/layout of an exemplary N-channel Junction-Field-Effect Transistor (JFET) 3 where JFET structure is cut perpendicular to a drain contact 141 and a source contact 143 along the JFET gates 137, 139. JFETs use a reverse-biased PN junction to control current flow by modulating a depletion field (e.g., depletion field lines 147) within a semi-conductive channel region (SCR) 145 (e.g., a higher reverse voltage extends depletion field outward restricting current flow in SCR 145). N-Channel JFETs use N Substrate 131 (e.g., N doped substrate). A conductive layer (e.g., metal) is disposed onto opposite sides of N substrate 131 forming a drain contact 141 on one side and a source contact 143 on the other side. A region of opposite doping of N substrate 131 is implanted/diffused in between drain and source in proximity to substrate middle forming two P body regions 133, 135, where P-body region in conjunction with the N substrate forms a PN junction. A conductive layer (e.g., metal) is disposed onto each P-body region forming JFET gate contacts 137, 139. P-channel JFETs (not shown) can be manufactured following similar steps but differs in design to an N-channel JFET 3 in that references to N doped regions (e.g., N epitaxial layer) become P doped regions (e.g., P epitaxial layer) and references to P doped regions (e.g., P body) become N doped regions (e.g., N body).
JFETs exhibit a natural hardness to TID effects; whereas TID effects in LDMOSFETs are caused by trapped charge in gate dielectric which in turn interferes with modulation of semi-conductive channel region. JFETs employ a depletion field to modulate a semi-conductive channel region and are not affected by trapped charge.
LDMOSFET transistors subjected to space-like environments or other particle-enriched environments are prone to SEGR and SEB, which can adversely affect a device's performance and can even cause catastrophic system failure. When a charge particle traverses a material, it sheds energy in accordance with its linear energy transfer (LET) function for that material and that energy can create electron-hole pairs along its path. In presence of an electric field, these electron-hole pairs can separate producing unwanted current flow. A resultant current flow under certain conditions can lead to SEB or SEGR. SEB can occur if particle-induced current flow turns on a parasitic bipolar transistor (parasitic bipolar is inherent to design of device) and can lead to thermal runaway (e.g., device fails catastrophically). SEGR can occur if particle-induced current flow disrupts the depletion field in the epitaxial layer under the gate coupling a portion of drain potential across gate dielectric sufficient to damage gate dielectric. SEB and SEGR mechanisms can be more complex than presented here but intent is to provide a cursory explanation of SEGR.
To address these and other disadvantages, embodiments of the invention are provided that include apparatuses and methods for modulating current/voltage response using multiple SCRs produced from different integrated semiconductor structures. For example, exemplary embodiments of the invention provide a structure offering operational performance to address various disadvantages associated with currently available transistors and provide desired improvements. In general, an embodiment of the invention includes an integrated combination of LDMOSFET and JFET functions operable to modulate current/voltage response or to mitigate electromagnetic or radiation interferences by altering current flow through either a LDMOSFET's semi-conductive channel region (SCR), through a JFET's SCR, or through both. For example, one embodiment of the invention, such as an exemplary Dual-Gate Lateral Diffused Metal-Oxide-Semiconductor Field Effect Transistor (DGLDMOSFET), can include a layout/design of an innovative dual gate structure integrating/combining structures of both, a LDMOSFET and a JFET transistor, allowing a drain-to-source current to be controlled by either a LDMOSFET gate, by a JFET gate, or by both. An exemplary DGLDMOSFET can be fabricated as a monolithic device integrating functions of a LDMOSFET transistor with functions of a JFET transistor into a monolithic structure providing characteristics that are unique in operation and performance to either transistor function.
Exemplary embodiments of the invention, e.g., DGLDMOSFET, can also enhance operational performance in a radiation environment (e.g., radiation environments prone to TID, SEB, and SEGR). An exemplary embodiment with an integrated JFET gate function can provide a radiation-hardened-by-design (RHBD) where an integrated JFET control gate continues to control a drain-to-source current flow beyond operational failure of an LDMOSFET control gate (e.g., JFET control gate can continue to control current in semi-conductive channel region if LDMOSFET control gate becomes non-functional (e.g., from TID-induced threshold voltage shifts)). An exemplary DGLDMOSFET can provide an enhanced barrier (e.g., JFET's depletion field region) that can limit a radiation particle's interaction with exemplary embodiments of the invention from suffering from SEB and SEGR conditions. An exemplary DGLDMOSFET can be useful in RF type applications such as mixers, gain control, amplifiers, and detectors because the exemplary device employs a second independent gate to control current flow in the semi-conductive channel region.
Radio-frequency (RF) applications such as RF mixers, RF amplifiers, RF gain control, and RF detectors can employ two individual transistors or can use a dual gate transistor in its circuit design. FIG. 4 shows two exemplary RF circuits where one design uses a dual gate transistor 161 and another uses two transistors 163. Circuits using two transistors instead of a dual gate transistor are less desirable due to added costs, weight and area.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of illustrative embodiment(s) exemplifying some best modes of carrying out the invention as presently perceived.